1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to an improvement of a flash write function of an image memory used as a frame buffer in the field of image processing or the like.
2. Description of the Background Art
In the field of data processing, generally the result of data processing is displayed on a CRT (Cathode Ray Tube). When a general purpose dynamic random access memory (DRAM) is used as a memory for displaying images, a CPU (Central Processing Unit) can not access to the DRAM while the images are displayed, since the DRAM is capable of only one of writing and reading of data in one cycle. Consequently, wait time of the CPU becomes longer, preventing high speed processing of data.
In view of the foregoing, a dual port RAM having a RAM port to which the CPU can access at a random sequence and a serial port (SAM port) for serially outputting image data to the CRT has come to be used as a memory for processing image information at high speed. FIG. 1 shows a schematic structure of a conventional general dual port RAM.
Referring to FIG. 1, the dual port RAM comprises a memory cell array 1 having memory cells arranged in a matrix of rows and columns, each cell storing information. Since the dual port RAM shown in FIG. 1 has a .times.4 bit structure (4 bit parallel input/output), the memory cell array 1 is divided into 4 blocks MB1, MB2, MB3 and MB4.
A row decoder 2 and a column decoder 8 are provided for selecting rows and columns of the memory cell array 1, respectively. The row decoder 2 decodes an internal row address Ax applied from an address buffer 18 to select one row of the memory cell array 1. Consequently, one row is selected from each of the memory cell array blocks MB1 to MB4.
The column decoder 8 decodes an internal column address Ay from the address buffer 18 to select a corresponding column of the memory cell array 1. On this occasion, since the dual port RAM has the .times.4 bit structure, one column is selected from each of the memory cell array blocks MB1 to MB4 by the output from the column decoder 8. The address buffer 18 receives externally applied address A0 to A8. Row addresses and column addresses have the externally applied address A0 to A8 applied time divisionally.
The columns of the memory cell array 1 selected by the column decoder 8 are connected to a RAM port 11. The RAM port 11 comprises an input/output buffer 110 for transferring data to and from the outside. 4 bit data W/IO1 to W/IO4 are inputted/outputted in parallel through the input/output buffer 110.
A color register 20 is provided for writing the same data in one row of memory cells selected by the row decoder 2 in the flash write mode.
A transfer gate 12, a data register 13, a serial data selector 14 and a serial port 15 are provided for serially outputting data of the memory cell array 1. The transfer gate 12 is formed of a series of transistors provided to each of the columns, which becomes conductive in an internal data transfer cycle to connect the memory cell array 1 with the data register 13. The data register 13 latches data transmitted through the transfer gate 12. The serial data selector 14 successively selects the data latched by the data register 13 in response to the address information from the address counter 16 to transmit the same to the serial port 15.
The serial port 15 comprises a serial output buffer 150. The serial output buffer 150 receives data (4 bit parallel data) selected by the serial data selector 14 and outputs the same as 4 bit serial data SO1 to SO4 in parallel.
The address counter 16 latches the column address Ay applied from the address buffer 18 and designates bit position of the data register 13 which is to be read at first from the serial data selector 14. Thereafter, the address is successively incremented in the address counter 16 in response to a clock signal SC.
The transfer gate 12, the data register 13 and the serial data selector 14 are respectively divided into four blocks corresponding to the memory cell array blocks MB1 to MB4, and they operate on a block basis, respectively. More specifically, the transfer gate 12 comprises transfer gate blocks 12-1 to 12-4; the data register 13 comprises data register blocks 13-1 to 13-4; and the serial data selector 14 comprises serial data selector blocks 14-1 to 14-4.
A timing generation circuit 19 is provided for generating control clocks defining various operation timings of the dual port RAM. The timing generating circuit 19 receives a row address strobe signal RAS applying a timing for taking row addresses, a column address strobe signal CAS applying a timing to take column addresses, a signal DT/OE activating data output in the RAM port and defining internal data transfer cycle, a signal WB/WE activating data writing in the RAM port and designating write per bit mode, and a signal F designating flash writing. Addresses A0 to A8 for refreshing are generated for designating row addresses for refreshing in the memory cell array 1 are generated from the timing generating circuit 19, which addresses are transmitted to the row decoder 2 through the address buffer 18.
A serial enable signal SOE for activating the serial port 15 is applied to the serial port 15. The operation will be briefly described in the following.
For example, a CPU accesses the memory cell array 1 through the RAM port 11, in the same manner as to a common DRAM. Writing/reading of data in the RAM port 11 is determined by the signals DT/OE and WB/WE. If the signal DT/OE is active, it is in the data output mode, and if the signal WB/WE is active, it is in the data writing mode.
Data transfer from the memory cell array 1 to the data register 13 is carried out by using the controlling signal DT/OE. If the signal DT/OE is "L" at the falling edge of the signal RAS changing to "L", the memory cell data of the row designated by the row address Ax taken at the falling edge of this signal RAS are transferred to the data register 13 through the transfer gate 12. The address counter 16 latches the column address Ay taken at the falling edge of the signal CAS and transmits the same to the serial data selector 14. The serial data selector 14 selects the data of the bit position corresponding to the column address from the address counter 16 from the data register 13 to transmit the same to the serial output buffer 150. The data output of the serial data selector 14 is done after the signal DT/OE has risen to complete internal data transfer. The address in the address counter 16 is successively incremented in response to the clock signal SC. Consequently, data are serially outputted from each of the blocks of the data register 13.
The write per bit operation will be described briefly. In the field of graphic processing or the like, it is sometimes necessary for the CPU to rewrite data on a bit basis in the memory. For example, if 4 bit data outputted from the serial port correspond to color signals R (red), G (green) and B (blue), sometimes only one of these colors is desired to be changed. In such a case, the write per bit operation is carried out to rewrite the desired color data only. In the write per bit operation, the signal WB/WE is set to "L" when the signal RAS falls. At this timing, only the data input terminal Wi to which "H" is applied becomes the write enable state. Thereafter, the signal WB/WE rises to "H" and the signal CAS falls and thereafter the signal WB/WE falls, whereby data are written only to the input terminal to which writing is enabled at the said timing.
When data of memory cells of one row are to be erased in the field of data processing, high speed erasure becomes possible by writing the same data to the selected row at one time. Such operation cycle is called a flash write operation. The data written to the selected row at this time are written to the color register 20. The flash write operation will be described in more detail in the following.
The path of data writing from the RAM port of 1 bit is schematically shown in FIG. 2. Referring to FIG. 2, a control gate 4 is provided between an internal data transmitting line 50 for transmitting write data Din and the memory cell array 1'. The control gate 4 comprises transistor switches Tr1 to Trn provided corresponding to respective columns of the memory cell array 1. The control gate 4 becomes conductive in response to the internal writing control signal WR. The internal writing control signal WR is generated from the timing generating circuit 19 shown in FIG. 1 in response to the write enable signal WB/WE. A sense amplifier 3 for detecting and amplifying data of the selected memory cell out of the memory cell array 1' is provided between the column decoder 8 and the memory cell array 1. The column decoder 8 receives the internal flash write designating signal F as an operation controlling signal. If the internal flash write designating signal F is active "L", the column decoder 8 sets all the outputs thereof to active "H", and connects all columns of the memory cell array 1 to the control gate 4. If the internal flash write designating signal F is inactive "H", it decodes the internal column address Ay in response to a prescribed timing (applied from the signal CAS) and selects a corresponding column from the memory cell array 1 to connect the same to the control gate 4.
In the flash write mode, the data Din transmitted to the internal write data transmitting line 50 are transmitted from the color register 20. The flash write operation will be described in the following with reference to the signal waveforms of FIG. 3.
Designation of the flash write operation is done by setting the write controlling signal WR (WB/WE) and the flash write enable signal F both to "L" at the falling edge of the signal RAS. Consequently, the color register 20 is activated, and the data applied to the RAM port 11 (see FIG. 1) are written to the color register 20 as the data for flash writing. At this time, the external address An (A0 to A8) taken to the address buffer 18 at the falling edge of the signal RAS is transmitted to the row decoder 2 as the row address Ax. Thereafter, the internal row address Ax is decoded by the row decoder 2, and one row of the memory cell array 1 is selected.
Meanwhile, when the write control signal WR becomes active "L", the switching transistors Tr1 to Trn of the control gate 4 all become conductive. Thereafter, when the signal CAS falls to "L", generally the internal column address Ay is decoded by the column decoder 8. However, in this mode, since the internal flash write designating signal F is active "L", the column decoder 8 set all outputs thereof to "H". Consequently, all the columns of the memory cell array 1 are connected to the internal data transmitting line 50 through the conductive control gate 4. The data are transmitted from the color register 20 to the internal data transmitting line 50 in response to the signal CAS, and the write data Din are written to all the memory cells of the selected row.
By the above described structure, it becomes possible to write data to one row of memory cells (for example 512 bits, or 2048 bits in a RAM having 1M bit capacity of .times.4 bit structure) at one time by one operation cycle, which enables clearing of the display screen at high speed.
By using a conventional flash write function, it is possible to clear the screen at high speed and it is also possible to rewrite data only of desired rows with respect to the vertical direction on a display screen.
Meanwhile, in the field of image processing, sometimes it becomes necessary to rewrite data of only a specified area with respect to the horizontal direction of the screen, such as in the case of window erasure in which a window area on the screen is erased or rewritten. Generally, respective bits of the memory correspond to respective dots on the screen such that one row of the dual port RAM corresponds to one horizontal scanning line on the screen. Therefore, when the flash write function described above is used, all memory cell data of one row are rewritten at one time, and accordingly, it is impossible to selectively rewrite data at a specified area in the horizontal direction.
General description of the flash write function is disclosed in pp. 123 to 129 of NIKKEI ELECTRONICS (No. 431) published on Oct. 5, 1987.
This reference discloses a block write function wherein one block of 4 rows and 4 columns (for .times.4 bit memory) or 8 rows and 4 columns (for .times.8 bit memory) is selected to have data written thereinto. In the block write mode, at the falling edge of the signal RAS, a row address applied at address pins is taken into the memory to be decoded for selecting 4 rows (for .times.4 bit memory). At the same time, data at data input/output pins are taken into the memory to define a bit or bits to be masked of the color register. Then a column address excluding the least significant bit is taken into the memory for selecting one column block of 4 bits at the falling edge of the signal CAS. At the same time, data at data input/output pins is taken into to define a column to be masked in the column block. Therefore, according to the block write mode, one block of 4.times.4 bits or 8.times.4 bits are subjected to data writing in one RAS cycle. This block write mode enables clear of the display screen on a block basis, but only 4 bits on a row can be accessed at a time.